The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a circuit within an integrated circuit device for testing the continuity of the input and output pins of the device.
In recent years, the density of semiconductor integrated circuit devices has increased substantially, both in regards to an increase in memory sizes and logic complexity and a decrease in device package sizes. This has resulted in integrated circuit devices having smaller pitches and higher lead counts. One resultant problem from this trend towards high density devices is that it is more difficult to ensure that all of the pins (input and output) of the device make solid contact in the socket or circuit board in which the device is to be programmed and tested. If the device pins are not making solid contact in the test socket or circuit board, then the subsequent testing and programming of the device could provide erroneous test results that might later lead to the failure of the device.
U.S. Pat. No. 5,983,377 to Knotts discloses a system and circuit for pin fault testing. The system includes an external tester and a circuit designed to be tested. The external tester is coupled to pins of the circuit and is configured to enter test data into the circuit. The external tester is also configured to receive continuity data from the circuit and to determine pin faults from a comparison of the test data to the continuity data. The circuit includes a plurality of scan cells which are coupled in a chain fashion. When testing input pins, the external tester places a test pattern onto the input pins, stores a continuity pattern into the scan cells that are electro-mechanically coupled to the input pins, serially scans the continuity pattern out of the circuit, and compares the continuity pattern to the test pattern. When testing the output pins, the external tester serially scans a test pattern into the scan cells coupled to the output pins and compares the continuity pattern generated on the output pins to the test pattern. It would be preferable to be able to test both the input and output pins at the same time. It would also be preferable to be able to optionally configure the IC device to be in a test mode as well as in its normal operating mode, without the need for specialized external test circuitry.
U.S. Pat. No. 4,825,414 to Kawata et al. discloses a semiconductor integrated circuit device having a normal mode and a test mode for testing internal memory blocks of the device. However, Kawata et al. does not discuss testing the continuity of the input and output pins of the device.
It is the object of the present invention to provide an integrated circuit device having an input/output continuity test mode circuit that can be used to ensure device-socket or device-board continuity for testing and programming.
The above object has been achieved by a continuity test mode circuit in an integrated circuit device having a means for switching between a continuity test mode and a normal operating mode, the test mode being characterized by one or more input pins being in direct electrical connection with one or more output pins to enable the pins of the chip package and chip socket or circuit board to be tested for continuity. In normal operating mode, the operation of the chip is not affected by the test mode circuitry.
In one embodiment of the invention, the normal input and output buffers are used with a multiplexer in between. The multiplexer connects the input buffer to the output buffer when the test mode is activated. Signals passing from an input pin through the input buffer will then pass straight through to the output buffer and an output pin. In normal mode, this direct connection is not made and the output buffer receives signals from the other parts of the device rather than directly from the input buffer.
In a second embodiment of the invention, additional input and output buffers, designated as test-mode buffers, are included in the circuit. These buffers are connected between the input and output pins, in parallel with the normal buffers, and are enabled only during the test mode.
The test mode circuit of the present invention allows all of the pins to be properly tested for solid contact in the programming socket or circuit board prior to initiating the programming cycle. Test signals can be placed on the input pins and then the signals generated on the output pins can be checked to determine whether proper contact has been made. The test mode circuit is included within the device, so no special external circuitry is needed to configure the device for testing. The test mode circuit can be activated on chip by way of a software command or similar means.